1. Field of the Invention
This invention relates to a method for growth of crystal, particularly to a method for growth of crystal which forms a crystalline film by crystallization of an amorphous film by solid phase growth.
2. Related Background Art
As one method in the field of crystal formation technique for growing a crystalline thin film on a substrate such as amorphous substrate, or the like, there has been proposed a method in which an amorphous thin film previously formed on a substrate is subjected to solid phase growth by annealing at a low temperature not higher than the melting point of the amorphous thin film. For example, there has been reported a crystal formation method in which an amorphous Si thin film with a film thickness of about 100 nm formed on an amorphous SiO.sub.2 surface is annealed at 600.degree. C. in N.sub.2 atmosphere to crystallize the above-mentioned amorphous Si thin film, whereby a polycrystalline thin film with a large grain size of about 5 .mu.m is formed (T. Noguchi, H. Hayashi and H. Ohshima, Mat. Res. Sos. Symp. Proc., 106, Polysilicon and Interfaces, 293, (Elsevier Science Publishing, New York, 1988)). The surface of the polycrystalline thin film obtained by this method remains flat and therefore can be formed as such into an electronic device such as an MOS transistor or diode. Also, since those devices thus obtained have polycrystals of larger than average grain sizes of polycrystals than the polycrystalline Si, etc. to be used by conventional Si IC process deposited by the LPCVD method, those having relatively higher performances can be obtained.
However, in the crystal formation method, although crystal grain sizes are large, their distribution and the position of the crystal grain boundary are not controlled. Since crystallization of the amorphous Si thin film is based on the solid phase growth of the crystal nuclei generated randomly within the amorphous by annealing, the positions of the grain boundaries are also formed randomly. As a result, the grain size will be distributed over a wide range. Therefore, the following problems to be described below arise for crystals with large average grain sizes.
For example, in MOS transistors, since the size of the gate becomes equal to or smaller than the average crystal grain size, and therefore portions containing no grain boundary and portions containing several boundaries will be formed at the gate portion. Electrical characteristics will change greatly between the portion containing no grain boundary and the portion containing several boundaries. Accordingly, a great variance will occur in the characteristics among a plurality of devices, and the variance in crystal grain size has been a significant obstacle in integrated circuit when forming an integrated circuit, or the like.
Attempts to solve the problems associated with large grain size polycrystalline thin film produced by the solid phase crystallization described above have been proposed. A method of inhibiting variance in grain size has been proposed in Japanese Laid-open Patent Application No. 58-56406. This method is described by use of FIG. 1. First, as shown in FIG. 1A, on the surface of an amorphous Si thin film 42 formed on an amorphous substrate 41, a small thin film strip 43 is provided, and the whole substrate is subjected to annealing in a conventional heating furnace. Then, nucleus formation of the crystal nucleus 44 occurs preferentially at the site in the amorphous Si thin film 42 where it contacts surrouding of the thin film strip 43. Accordingly, when the crystal nucleus is further permitted to grow, the amorphous Si thin film 42 is crystallized over the entire region to provide a polycrystalline thin film comprising a group of crystal grains 45 with large grains sizes as shown in FIG. 1B. According to the above-mentioned Japanese Laid-open Patent Application No. 58-56406, it is stated that the variance in grain size can be reduced in this method to about 1/3 as compared with the method of the prior art as described above.
However, even such result is still insufficient. For example, when thin film strips 43 are arranged in lattice shape with intervals of 10 .mu.m, the variance in grain size can be controlled only within the range of 3 to 8 .mu.m. Further, concerning control of the crystal grain boundary position, substantially no control has been attained under the present situation. The reason is that, because preferential nucleus formation occurs around the thin film strip 43 due to the localized effect of elastic energy at the portion where the amorphous Si thin film 42 contacts the surrounding of the thin film strip 43, a plurality of nuclei are generated along the surrounding and also its number can be controlled with difficulty.
Concerning the method of controlling the nucleation position in the solid phase growth of amorphous Si thin film, there is another proposal in Japanese Laid-open Patent Application No. 63-253616. As shown in FIG. 2(53 represents ions other than Si and 54 is a region injected with ions), in that methods, region 54 injected with ions 53 other than Si is provided locally at the amorphous Si thin film 52 on the amorphous substrate 51, and crystal nuclei are generated preferentially there. As the ions 53 other than Si, N and B have been proposed. However, in such method actual selectivity concerning nucleation is deficient between the region 54 injected with ions and other regions. Further, there has been no report of the practicality of the method.